Current sensing circuits using so-called current sensing transistors (or “sense FETs”) have been commonly used for years. Such current sensing techniques may be especially useful when measuring the load current of power field effect transistors (power FETs) which are composed of a plurality of transistor cells as illustrated, for example, in U.S. Pat. No. 6,847,091, granted Jan. 25, 2005 to Deboy et al., the entire contents of which is incorporated herein by reference. Such power field effect transistors have a common drain region for all transistors cells composing the power transistor component. The common drain region is connected by one drain electrode arranged on the back-side of a wafer, whereas the source region and the respective source electrodes are contacted on the front-side of the wafer and connected in parallel. The source electrode of one transistor cell (referred to as “sense cell”) may be separately connected to tap a current signal that is representative of the load current flowing through the plurality of transistor cells of the load transistor. In a circuit arrangement including a load transistor/sense transistor pair, the source current of the sense transistor is directly proportional to the source current of the load transistor whereby the factor of proportionality results from the ratio of the current conducting area of the load transistor and the current conducting area of the sense transistor.
The proportionality condition mentioned above is only met when both transistors (load transistor and sense transistor) operate in the same operating point, i.e., when both transistors are supplied with the same gate-source voltage and are exposed to the same drain-source voltage. U.S. Pat. No. 8,373,449, granted on Feb. 12, 2013 to Thiele et al., the entire contents of which are incorporated herein by reference, is addressed to a current sensing circuit arrangement where a load transistor and a sense transistor have a common source electrode and a common gate voltage. A closed loop operational amplifier circuit is arranged to equalize the drain voltages of the load transistor and the sense transistor.
FIG. 1 illustrates a high level schematic diagram of a current sensing circuit arrangement 10 according to the prior art. Arrangement 10 comprises: a main electronically controlled switch 20, hereinafter termed “main switch 20” for brevity; a sense electronically controlled switch 30, hereinafter termed “sense switch 30” for brevity; a voltage matching circuit 35, comprising an amplifier 40, implemented without limitation as an operational amplifier (op-amp), and an electronically controlled switch 50, hereinafter termed “switch 50” for brevity; a current mirror 60, comprising an input electronically controlled switch 70, herein after termed “input switch 70” for brevity, and an output electronically controlled switch 80, herein after termed “output switch 80” for brevity; and a sense impedance element, illustrated as a sense resistor RS. Each of main switch 20, sense switch 30 and switch 50 are illustrated as an n-channel metal-oxide-semiconductor field-effect-transistor (NMOSFET), however this is not meant to be limiting in any way. Each of input switch 70 and output switch 80 are illustrated as a p-channel metal-oxide-semiconductor field-effect-transistor (PMOSFET), however this is not meant to be limiting in any way.
The gates of main switch 20 and sense switch 30 are coupled to a common gate voltage, denoted VG, and the sources of main switch 20 and sense switch 30 are coupled to a common potential. The drain of main switch 20 is coupled to the non-inverting input of op-amp 40 and the inverting input of op-amp 40 is coupled to the drain of sense switch 30 and the source of switch 50. The output of op-amp 40 is coupled to the gate of switch 50. The drain of switch 50 is coupled to the drain of input switch 70 and to the gates of input switch 70 and output switch 80. The sources of input switch 70 and output switch 80 are coupled to a supply voltage, denoted VMAIN. The drain of output switch 80 is coupled to a first end of sense resistor RS and a second end of sense resistor RS is coupled to the common potential. A first end of a load 90 is coupled to the drain of main switch 20 and a second end of load 90 is coupled to supply voltage VMAIN.
In operation, main switch 20 is at least partially closed by common gate voltage VG to provide a current path for a load current, denoted ILOAD, generated responsive to load 90, the drain-source voltage of main switch 20 responsive to the magnitude of load current ILOAD and voltage drop across load 90. The operation of op-amp 40 and switch 50 of voltage matching circuit 35 causes the potential at the drain of sense switch 30 to be equal to the potential at the drain of main switch 20. As a result of the equality of the potential at the drain of sense switch 30 with the potential at the drain of main switch 20, the equality of the potential at the source of sense switch 30 with the potential at the source of main switch 20, and the equality of the potential at the gate of sense switch 30 with the potential at the gate of main switch 20, a sense current, denoted IS, is generated within sense switch 30, the magnitude of sense current IS being directly proportional to the magnitude of current ILOAD. The ratio of the magnitudes of sense current IS and load current ILOAD is equal to the ratio of the areas of main switch 20 and sense switch 30. Sense current IS is received by input switch 70 of current mirror 60 and a mirrored current, denoted ISENSE, is generated by output switch 80. The magnitude of current ISENSE is directly proportional to the magnitude of sense current IS, the ratio of the magnitudes being equal to the ratio of the area of output switch 80 and the area of input switch 70. The magnitude of current ISENSE is thus directly proportional to the magnitude of current ILOAD, i.e.:ISENSE=ILOAD*K  EQ. 1where K equals the area ratio of main switch 20 and sense switch 30 times the area ratio of input switch 70 and output switch 80. A voltage is developed across sense resistor RS responsive to current ISENSE flowing therethrough. The developed voltage can be used for measuring load current ILOAD responsive to EQ. 1.
Unfortunately, op-amp 40 exhibits an input offset voltage error, typically on the order of several tens of millivolts. The equalization of the potentials at the drains of main switch 20 and sense switch 30, and as a result the equalization of the drain-source voltages of main switch 20 and sense switch 30 is thus only accurate to within a predetermined error range. Therefore, there is a difference between the magnitude of current ISENSE and the magnitude of current ILOAD times constant K, the error denoted E. In the event that the magnitude of ILOAD is very small and the on-resistance of main switch 20 is very small, the drain-source voltage of main switch 20 will also be very small and the offset voltage error of op-amp 40 may be significant in relation to the drain-source voltage of main switch 20, i.e. the error in the equalization of the drain-source voltages of main switch 20 and sense switch 30 will be a significant percentage of the drain-source voltage of main switch 20. Therefore, error E will be a significant percentage of current ILOAD, rendering current ISENSE useless for providing an accurate measurement of load current ILOAD.